A Survey on Static Power Reduction Techniques in Asynchronous Circuits

With the technology down scaling the area of each device in a chip reduces. Lesser area increases the power consumption. In current technologies leakage current is the major part in power consumption. Power gating is a technique which has been used to reduce leakage power by shutting off the power when no activity done by the logic. These helps to reduce the power consumption, delay and switching times of the logic. This survey paper mentions the different techniques to reduce leakage power in asynchronous logic.